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8-bit microcontroller with 4 kbytes flash at89C51 features compatible with mcs-51 ? ? products 4 kbytes of in-system reprogrammable flash memory endurance: 1,000 write/erase cycles fully static operation: 0 hz to 24 mhz three-level program memory lock 128 x 8-bit internal ram 32 programmable i/o lines two 16-bit timer/counters six interrupt sources programmable serial channel low power idle and power down modes p1.0 v cc p1.1 p0.0 (ad0) p1.2 ()p3.2 int0 ale/prog ()p3.7 rd p2.3 (a11) (txd) p3.1 ea/vpp ()p3.6 wr p2.4 (a12) (rxd) p3.0 p0.7 (ad7) (t1) p3.5 p2.6 (a14) rst p0.6 (ad6) p1.7 p0.5 (ad5) p1.6 p0.4 (ad4) p1.5 p0.3 (ad3) p1.4 p0.2 (ad2) p1.3 p0.1 (ad1) ()p3.3 int1 psen xtal2 p2.2 (a10) (t0) p3.4 p2.7 (a15) xtal1 p2.1 (a9) gnd p2.0 (a8) p2.5 (a13) 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 22 23 24 25 26 40 39 38 37 36 35 34 33 32 31 30 29 28 27 pin configurations pdip/cerdip description the at89C51 is a low-power, high-performance cmos 8-bit microcomputer with 4 kbytes of flash programmable and erasable read only memory (perom). the device is manufactured using atmels high density nonvolatile memory technology and is compatible with the industry standard mcs-51 ? instruction set and pinout. the on-chip flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. by combining a versatile 8-bit cpu with flash on a monolithic chip, the atmel at89C51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. (continued) 23 1 index corner 34 p1.0 vcc p1.1 p1.2 p1.4 p1.3 nc 42 43 40 41 6 5 4 44 3 2 26 25 28 27 24 18 19 20 21 22 p1.7 p1.6 p1.5 nc 7 8 9 10 11 12 13 14 15 16 17 29 30 39 38 37 36 35 33 32 31 nc psen xtal1 gnd xtal2 gnd p0.0 (ad0) ale/prog ()p3.7 rd ea/vpp ()p3.6 wr (rxd) p3.0 p0.7 (ad7) p2.6 (a14) p0.6 (ad6) p0.5 (ad5) p0.4 (ad4) p0.3 (ad3) p0.2 (ad2) p0.1 (ad1) ()p3.2 int0 (txd) p3.1 (t1) p3.5 ()p3.3 int1 (t0) p3.4 p2.7 (a15) (a11) p2.3 (a12) p2.4 (a10) p2.2 (a9) p2.1 (a8) p2.0 rst p2.5 (a13) pqfp/tqfp p1.0 vcc p1.1 p0.0 (ad0) p1.2 ale/prog ()p3.7 rd xtal1 ea/vpp ()p3.6 wr gnd (rxd) p3.0 p0.7 (ad7) p2.6 (a14) p0.6 (ad6) p0.5 (ad5) p0.4 (ad4) p0.3 (ad3) p1.4 p0.2 (ad2) p1.3 p0.1 (ad1) psen xtal2 ()p3.2 int0 (txd) p3.1 (t1) p3.5 ()p3.3 int1 (t0) p3.4 p2.7 (a15) (a11) p2.3 (a12) p2.4 (a10) p2.2 (a9) p2.1 (a8) p2.0 nc 23 1 rst p1.7 p1.6 p1.5 index corner nc nc p2.5 (a13) 34 nc 42 43 40 41 6 5 444 3 2 26 25 28 27 18 19 20 24 21 22 7 8 9 10 11 12 13 14 15 16 17 29 30 39 38 37 36 35 33 32 31 plcc/lcc 0265e
port 2 drivers port 2 latch p2.0 - p2.7 flash port 0 latch ram program address register buffer pc incrementer program counter dptr ram addr. register instruction register b register interrupt, serial port, and timer blocks stack pointer acc tmp2 tmp1 alu psw timing and control port 3 latch port 3 drivers p3.0 - p3.7 port 1 latch port 1 drivers p1.0 - p1.7 osc gnd v cc psen ale/prog ea / v pp rst port 0 drivers p0.0 - p0.7 block diagram 2 at89C51
pin description v cc supply voltage. gnd ground. port 0 port 0 is an 8-bit open drain bidirectional i/o port. as an output port each pin can sink eight ttl inputs. when 1s are written to port 0 pins, the pins can be used as high-im- pedance inputs. port 0 may also be configured to be the multiplexed low- order address/data bus during accesses to external pro- gram and data memory. in this mode p0 has internal pul- lups. port 0 also receives the code bytes during flash program- ming, and outputs the code bytes during program verifica- tion. external pullups are required during program verifica- tion. port 1 port 1 is an 8-bit bidirectional i/o port with internal pullups. the port 1 output buffers can sink/source four ttl inputs. when 1s are written to port 1 pins they are pulled high by the internal pullups and can be used as inputs. as inputs, port 1 pins that are externally being pulled low will source current (i il ) because of the internal pullups. port 1 also receives the low-order address bytes during flash programming and program verification. port 2 port 2 is an 8-bit bidirectional i/o port with internal pullups. the port 2 output buffers can sink/source four ttl inputs. when 1s are written to port 2 pins they are pulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (i il ) because of the internal pullups. port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx the at89C51 provides the following standard features: 4 kbytes of flash, 128 bytes of ram, 32 i/o lines, two 16-bit timer/counters, a five vector two-level interrupt architec- ture, a full duplex serial port, on-chip oscillator and clock circuitry. in addition, the at89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/count- ers, serial port and interrupt system to continue function- ing. the power down mode saves the ram contents but freezes the oscillator disabling all other chip functions until the next hardware reset. description (continued) @ dptr). in this application it uses strong internal pullups when emitting 1s. during accesses to external data mem- ory that use 8-bit addresses (movx @ ri), port 2 emits the contents of the p2 special function register. port 2 also receives the high-order address bits and some control signals during flash programming and verification. port 3 port 3 is an 8-bit bidirectional i/o port with internal pullups. the port 3 output buffers can sink/source four ttl inputs. when 1s are written to port 3 pins they are pulled high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (i il ) because of the pullups. port 3 also serves the functions of various special features of the at89C51 as listed below: port pin alternate functions p3.0 rxd (serial input port) p3.1 txd (serial output port) p3.2 int0 (extenal interrupt 0) p3.3 int1 (extenal interrupt 1) p3.4 t0 (timer 0 extenal input) p3.5 t1 (timer 1 external input) p3.6 wr (extenal data memory write strobe) p3.7 rd (external data memory read strobe) port 3 also receives some control signals for flash pro- gramming and programming verification. rst reset input. a high on this pin for two machine cycles while the oscillator is running resets the device. ale/ prog address latch enable output pulse for latching the low byte of the address during accesses to external memory. this pin is also the program pulse input ( prog) during flash programming. in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is weakly pulled high. setting the ale-disable bit has no ef- fect if the microcrontroller is in external execution mode. psen program store enable is the read strobe to external pro- gram memory. (continued) at89C51 3
oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 1. either a quartz crystal or ceramic resonator may be used. to drive the device from an external clock source, xtal2 should be left unconnected while xtal1 is driven as shown in figure 2. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifi- cations must be observed. idle mode in idle mode, the cpu puts itself to sleep while all the on- chip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the spe- cial functions registers remain unchanged during this figure 2. external clock drive configuration c2 xtal2 gnd xtal1 c1 figure 1. oscillator connections notes: c1, c2 = 30 pf 10 pf for crystals = 40 pf 10 pf for ceramic resonators status of external pins during idle and power down mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 data data data data idle external 1 1 float data address data power down internal 0 0 data data data data power down external 0 0 float data data data when the at89C51 is executing code from external pro- gram memory, psen is activated twice each machine cy- cle, except that two psen activations are skipped during each access to external data memory. ea/v pp external access enable. ea must be strapped to gnd in order to enable the device to fetch code from external pro- gram memory locations starting at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, ea will be internally latched on reset. ea should be strapped to v cc for internal program execu- tions. this pin also receives the 12-volt programming enable voltage (v pp ) during flash programming, for parts that re- quire 12-volt v pp . xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. pin description (continued) mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset. it should be noted that when idle is terminated by a hard- ware reset, the device normally resumes program execu- tion, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hard- 4 at89C51
ware inhibits access to internal ram in this event, but ac- cess to the port pins is not inhibited. to eliminate the pos- sibility of an unexpected write to a port pin when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. power down mode in the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. the on-chip ram and special function regis- ters retain their values until the power down mode is termi- nated. the only exit from power down is a hardware reset. reset redefines the sfrs but does not change the on- chip ram. the reset should not be activated before v cc is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. program memory lock bits on the chip are three lock bits which can be left unpro- grammed (u) or can be programmed (p) to obtain the ad- ditional features listed in the table below: when lock bit 1 is programmed, the logic level at the ea pin is sampled and latched during reset. if the device is powered up without a reset, the latch initializes to a ran- dom value, and holds that value until reset is activated. it is necessary that the latched value of ea be in agreement with the current logic level at that pin in order for the device to function properly. programming the flash the at89C51 is normally shipped with the on-chip flash memory array in the erased state (that is, contents = ffh) and ready to be programmed. the programming interface accepts either a high-voltage (12-volt) or a low-voltage (v cc ) program enable signal. the low voltage program- ming mode provides a convenient way to program the at89C51 inside the users system, while the high-voltage programming mode is compatible with conventional third party flash or eprom programmers. the at89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. the respective top-side marking and device signature codes are listed in the following table. v pp = 12 v v pp = 5 v top-side mark at89C51 at89C51 xxxx xxxx-5 yyww yyww signature (030h)=1eh (030h)=1eh (031h)=51h (031h)=51h (032h)=ffh (032h)=05h the at89C51 code memory array is programmed byte- by-byte in either programming mode. to program any non-blank byte in the on-chip flash memory, the entire memory must be erased using the chip erase mode. programming algorithm: before programming the at89C51, the address, data and control signals should be set up according to the flash programming mode table and figures 3 and 4. to program the at89C51, take the following steps. 1. input the desired memory location on the address lines. 2. input the appropriate data byte on the data lines. 3. activate the correct combination of control signals. 4. raise ea/v pp to 12 v for the high-voltage program- ming mode. 5. pulse ale/ prog once to program a byte in the flash array or the lock bits. the byte-write cycle is self-timed and typically takes no more than 1.5 ms. repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. data polling: the at89C51 features data polling to indi- cate the end of a write cycle. during a write cycle, an at- ( c ontinued ) lock bit protection modes program lock bits lb1 lb2 lb3 protection type 1 u u u no program lock features. 2puu movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the flash is disabled. 3 p p u same as mode 2, also verify is disabled. 4 p p p same as mode 3, also external execution is disabled. at89C51 5
tempted read of the last byte written will result in the com- plement of the written datum on po.7. once the write cy- cle has been completed, true data are valid on all outputs, and the next cycle may begin. data polling may begin any time after a write cycle has been initiated. ready/ busy: the progress of byte programming can also be monitored by the rdy/ bsy output signal. p3.4 is pulled low after ale goes high during programming to in- dicate busy. p3.4 is pulled high again when program- ming is done to indicate ready. program verify: if lock bits lb1 and lb2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. the lock bits cannot be verified directly. verification of the lock bits is achieved by observing that their features are en- abled. chip erase: the entire flash array is erased electrically by using the proper combination of control signals and by holding ale/ prog low for 10 ms. the code array is writ- ten with all 1"s. the chip erase operation must be exe- cuted before the code memory can be re-programmed. reading the signature bytes: the signature bytes are read by the same procedure as a normal verification of locations 030h, 031h, and 032h, except that p3.6 and p3.7 must be pulled to a logic low. the values returned are as follows. (030h) = 1eh indicates manufactured by atmel (031h) = 51h indicates 89C51 (032h) = ffh indicates 12 v programming (032h) = 05h indicates 5 v programming programming interface every code byte in the flash array can be written and the entire array can be erased by using the appropriate com- bination of control signals. the write operation cycle is self-timed and once initiated, will automatically time itself to completion. all major programming vendors offer worldwide support for the atmel microcontroller series. please contact your local programming vendor for the appropriate software re- vision. flash programming modes mode rst psen ale/ ea/ v pp p2.6 p2.7 p3.6 p3.7 prog write code data h l h/12v (1) lhhh read code data h l h h l l h h write lock bit - 1 h l h/12v h h h h bit - 2 h l h/12v h h l l bit - 3 h l h/12v h l h l chip erase h l h/12v h l l l read signature byte h l h h l l l l notes: 1. the signature byte at location 032h designates whether v pp = 12 v or v pp = 5 v should be used to enable programming. 2. chip erase requires a 10 ms prog pulse. (2) programming the flash (continued) 6 at89C51
flash programming and verification characteristics t a = 21c to 27c, v cc = 5.0 10% symbol parameter min max units v pp (1) programming enable voltage 11.5 12.5 v i pp (1) programming enable current 1.0 ma 1/t clcl oscillator frequency 4 24 mhz t avgl address setup to prog low 48t clcl t ghax address hold after prog 48t clcl t dvgl data setup to prog low 48t clcl t ghdx data hold after prog 48t clcl t ehsh p2.7 ( enable) high to v pp 48tclcl t shgl v pp setup to prog low 10 m s t ghsl (1) v pp hold after prog 10 m s t glgh prog width 1 110 m s t avqv address to data valid 48tclcl t elqv enable low to data valid 48t clcl t ehqv data float after enable 0 48t clcl t ghbl prog high to busy low 1.0 m s t wc byte write cycle time 2.0 ms note: 1. only used in 12-volt programming mode. p1 p2.6 p3.6 p2.0 - p2.3 a0 - a7 addr. ooooh/0fffh see flash programming modes table 4-24 mhz a8 - a11 p0 +5v p2.7 pgm data (use 10k pullups) v ih v ih ale p3.7 xtal 2 ea rst psen xtal 1 gnd v cc at89C51 figure 4. verifying the flash p1 p2.6 p3.6 p2.0 - p2.3 a0 - a7 addr. ooooh/offfh see flash programming modes table 4-24 mhz a8 - a11 p0 +5v p2.7 pgm data prog v/v ih pp v ih ale p3.7 xtal 2 ea rst psen xtal 1 gnd v cc at89C51 figure 3. programming the flash at89C51 7
t glgh t avgl t shgl t dvgl t ghax t avqv t ghdx t ehsh t elqv t wc busy ready t ghbl t ehqz p1.0 - p1.7 p2.0 - p2.3 ale/prog port 0 logic 1 logic 0 ea/v pp p2.7 (enable) p3.4 (rdy/bsy) programming address verification address data i n data o u t flash programming and verification waveforms - low voltage mode t glgh t ghsl t avgl t shgl t dvgl t ghax t avqv t ghdx t ehsh t elqv t wc busy ready t ghbl t ehqz p1.0 - p1.7 p2.0 - p2.3 ale/prog port 0 logic 1 logic 0 ea/v pp v pp p2.7 (enable) p3.4 (rdy/bsy) programming address verification address data i n data o u t flash programming and verification waveforms - high voltage mode 8 at89C51
d.c. characteristics t a = -40c to 85c, v cc = 5.0 v 20% (unless otherwise noted) symbol parameter condition min max units v il input low voltage (except ea) -0.5 0.2 v cc -0.1 v v il1 input low voltage ( ea) -0.5 0.2 v cc -0.3 v v ih input high voltage (except xtal1, rst) 0.2 v cc +0.9 v cc +0.5 v v ih1 input high voltage (xtal1, rst) 0.7 v cc v cc +0.5 v v ol output low voltage (1) (ports 1,2,3) i ol = 1.6 ma 0.45 v v ol1 output low voltage (1) (port 0, ale, psen) i ol = 3.2 ma 0.45 v v oh output high voltage (ports 1,2,3, ale, psen) i oh = -60 m a, v cc = 5 v 10% 2.4 v i oh = -25 m a 0.75 v cc v i oh = -10 m a 0.9 v cc v v oh1 output high voltage (port 0 in external bus mode) i oh = -800 m a, v cc = 5 v 10% 2.4 v i oh = -300 m a 0.75 v cc v i oh = -80 m a 0.9 v cc v i il logical 0 input current (ports 1,2,3) v in = 0.45 v -50 m a i tl logical 1 to 0 transition current (ports 1,2,3) v in = 2 v -650 m a i li input leakage current (port 0, ea) 0.45 < v in < v cc 10 m a rrst reset pulldown resistor 50 300 k w c io pin capacitance test freq. = 1 mhz, t a = 25c 10 pf i cc power supply current active mode, 12 mhz 20 ma idle mode, 12 mhz 5 ma power down mode (2) v cc = 6 v 100 m a v cc = 3 v 40 m a operating temperature................... -55c to +125c storage temperature...................... -65c to +150c voltage on any pin with respect to ground ................... -1.0 v to +7.0 v maximum operating voltage ............................ 6.6 v dc output current ....................................... 15.0 ma *notice: stresses beyond those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings* notes: 1. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin:10 ma maximum i ol per 8-bit port: port 0:26 ma ports 1,2, 3:15 ma maximum total iol for all output pins:71 ma if iol exceeds the test condition, vol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. minimum vcc for power down is 2 v. at89C51 9
external program and data memory characteristics symbol parameter 12 mhz oscillator 16 to 24 mhz oscillator units min max min max 1/t clcl oscillator frequency 0 24 mhz t lhll ale pulse width 127 2t clcl -40 ns t avll address valid to ale low 28 tclcl-13 ns t llax address hold after ale low 48 tclcl-20 ns t lliv ale low to valid instruction in 233 4tclcl-65 ns t llpl ale low to psen low 43 t clcl -13 ns t plph psen pulse width 205 3t clcl -20 ns t pliv psen low to valid instruction in 145 3t clcl -45 ns t pxix input instruction hold after psen 0 0 ns t pxiz input instruction float after psen 59 t clcl -10 ns t pxav psen to address valid 75 t clcl -8 ns t aviv address to valid instruction in 312 5t clcl -55 ns t plaz psen low to address float 10 10 ns t rlrh rd pulse width 400 6t clcl -100 ns t wlwh wr pulse width 400 6t clcl -100 ns t rldv rd low to valid data in 252 5t clcl -90 ns t rhdx data hold after rd 0 0 ns t rhdz data float after rd 97 2t clcl -28 ns t lldv ale low to valid data in 517 8tclcl-150 ns t avdv address to valid data in 585 9tclcl-165 ns t llwl ale low to rd or wr low 200 300 3t clcl -50 3t clcl +50 ns t avwl address to rd or wr low 203 4t clcl -75 ns t qvwx data valid to wr transition 23 t clcl -20 ns t qvwh data valid to wr high 433 7t clcl -120 ns t whqx data hold after wr 33 t clcl -20 ns t rlaz rd low to address float 0 0 ns t whlh rd or wr high to ale high 43 123 t clcl -20 t clcl +25 ns a.c. characteristics (under operating conditions; load capacitance for port 0, ale/ prog, and psen = 100 pf; load capacitance for all other outputs = 80 pf) 10 at89C51
t lhll t lldv t llwl t llax t whlh t avll t rlrh t avdv t avwl t rlaz t rhdx t rldv t rhdz a0 - a7 from ri or dpl ale psen rd port 0 port 2 p2.0 - p2.7 or a8 - a15 from dph a0 - a7 from pcl a8 - a15 from pch data in instr in external data memory read cycle t lhll t lliv t pliv t llax t pxiz t plph t plaz t pxav t avll t llpl t aviv t pxix ale psen port 0 port 2 a8 - a15 a0 - a7 a0 - a7 a8 - a15 instr in external program memory read cycle at89C51 11
external clock drive symbol parameter min max units 1/t clcl oscillator frequency 0 24 mhz t clcl clock period 41.6 ns t chcx high time 15 ns t clcx low time 15 ns t clch rise time 20 ns t chcl fall time 20 ns t chcx t chcx t clcx t clcl t chcl t clch v - 0.5v cc 0.45v 0.2 v - 0.1v cc 0.7 v cc external clock drive waveforms t lhll t llwl t llax t whlh t avll t wlwh t avwl t qvwx t qvwh t whqx a0 - a7 from ri or dpl ale psen wr port 0 port 2 p2.0 - p2.7 or a8 - a15 from dph a0 - a7 from pcl a8 - a15 from pch data out instr in external data memory cycle 12 at89C51
t xhdv t qvxh t xlxl t xhdx t xhqx ale input data clear ri output data write to sbuf instruction clock 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 set ti set ri 8 valid valid valid valid valid valid valid valid shift register mode timing waveforms 0.45v test points v - 0.5v cc 0.2 v + 0.9v cc 0.2 v - 0.1v cc ac testing input/output waveforms (1) note: 1. ac inputs during testing are driven at v cc - 0.5 v for a logic 1 and 0.45 v for a logic 0. timing measure- ments are made at v ih min. for a logic 1 and v il max. for a logic 0. serial port timing: shift register mode test conditions (v cc = 5.0 v 20%; load capacitance = 80 pf) symbol parameter 12 mhz osc variable oscillator units min max min max t xlxl serial port clock cycle time 1.0 12t clcl m s t qvxh output data setup to clock rising edge 700 10t clcl -133 ns t xhqx output data hold after clock rising edge 50 2t clcl -33 ns t xhdx input data hold after clock rising edge 0 0 ns t xhdv clock rising edge to input data valid 700 10tclcl-133 ns v load + 0.1v timing reference points v load - 0.1v load v v ol + 0.1v v ol - 0.1v float waveforms (1) note: 1. for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs. a port pin begins to float when a 100 mv change from the loaded v oh /v ol level occurs. at89C51 13
ordering information speed (mhz) power supply ordering code package operation range 12 5 v 20% at89C51-12ac 44a commercial at89C51-12jc 44j (0 c to 70 c) at89C51-12pc 40p6 at89C51-12qc 44q at89C51-12ai 44a industrial at89C51-12ji 44j (-40 c to 85 c) at89C51-12pi 40p6 at89C51-12qi 44q at89C51-12aa 44a automotive at89C51-12ja 44j (-40 c to 125 c) at89C51-12pa 40p6 at89C51-12qa 44q 5 v 10% at89C51-12dm 40d6 military at89C51-12lm 44l (-55 c to 125 c) at89C51-12dm/883 40d6 military/883c at89C51-12lm/883 44l class b, fully compliant (-55 c to 125 c) 16 5 v 20% at89C51-16ac 44a commercial at89C51-16jc 44j (0 c to 70 c) at89C51-16pc 40p6 at89C51-16qc 44q at89C51-16ai 44a industrial at89C51-16ji 44j (-40 c to 85 c) at89C51-16pi 40p6 at89C51-16qi 44q at89C51-16aa 44a automotive at89C51-16ja 44j (-40 c to 125 c) at89C51-16pa 40p6 at89C51-16qa 44q 20 5 v 20% at89C51-20ac 44a commercial at89C51-20jc 44j (0 c to 70 c) at89C51-20pc 40p6 at89C51-20qc 44q at89C51-20ai 44a industrial at89C51-20ji 44j (-40 c to 85 c) at89C51-20pi 40p6 at89C51-20qi 44q 14 at89C51
ordering information package type 44a 44 lead, thin plastic gull wing quad flatpack (tqfp) 40d6 40 lead, 0.600" wide, non-windowed, ceramic dual inline package (cerdip) 44j 44 lead, plastic j-leaded chip carrier (plcc) 44l 44 pad, non-windowed, ceramic leadless chip carrier (lcc) 40p6 40 lead, 0.600" wide, plastic dual inline package (pdip) 44q 44 lead, plastic gull wing quad flatpack (pqfp) speed (mhz) power supply ordering code package operation range 24 5 v 20% at89C51-24ac 44a commercial at89C51-24jc 44j (0 c to 70 c) at89C51-24pc 44p6 at89C51-24qc 44q at89C51-24ai 44a industrial at89C51-24ji 44j (-40 c to 85 c) at89C51-24pi 44p6 at89C51-24qi 44q at89C51 15

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